Although many types of logic circuits have been contemplated and fabricated using semiconductors, one of special interest for today's technology relies on complementary symmetry and, as implemented in silicon, is referred to by those skilled in the art as a CMOS device. The essential features of the CMOS device are two field effect transistors with one transistor being a p-channel device and the other transistor being an n-channel device. For simplest circuit operation, the transistors should have similar operating characteristics. Hence, the term complementary is appropriate. The two transistors are typically manufactured adjacent each other on a common substrate. The CMOS device can be wired so that it functions as a logic gate as, for example, an inverter. Of course, logic gates other than inverters may also be fabricated.
CMOS has the advantageous feature of having relatively small power dissipation as compared to other logic circuit technologies. This is true because one of the FETs is typically off and the current drawn by that FET is nominally zero. Additional advantages over other logic circuits typically include shorter propagation delays as well as better rise and fall time characteristics.
While implementation of the CMOS structures in silicon is now generally well understood by those skilled in the art, implementation of a complementary symmetry structure in materials other than silicon, such as Group III-V compound semiconductors, would in many cases be desirable because the carrier mobilities in such semiconductors are often significantly higher than they are in silicon. The higher carrier mobilities hold promise of such desirable device characteristics as faster operation. One such Group III-V semiconductor is GaAs.
However, fabrication of complementary symmetry structures in GaAs has been difficult for several reasons. Although the electron mobility is significantly higher in Si than it is in GaAs, the hole mobilities in the two semiconductors are roughly comparable. As a result, the p-channel transistor is much slower and has much poorer current-voltage characteristics than does the n-channel transistor. Consequently, many of the potential advantages of the complementary structure are not realized. Additionally, the gate structure for the p-channel device is typically formed by a schottky barrier thus forming a MESFET (metal semiconductor field effect transistor). Unfortunately, the barrier is relatively low.
Yet another approach to improving device performance relies on a judicious choice of structures rather than material. One such approach is termed modulation doping. A modulation doped heterostructure separates carriers from ionized parent impurities by doping a wide bandgap semiconductor and leaving the adjacent narrow bandgap semiconductor with intrinsic conductivity. A two-dimensional carrier system then is created, which depending on the dopant, will comprise electrons or holes. Modulation doped heterostructures have not yet been successfully used in CMOS structures.